A MRMDF FFT processor for MIMO OFDM applications

Yu Wei Lin*, Wan Chun Liao, Chen Yi Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, the proposed pipelined FFT processor, which is based on MRMDF structure, can deal with the simultaneous multiple input sequences more efficiently for MIMO OFDM applications. Furthermore, the hardware costs of memory and complex multipliers in our method can be saved by means of delay feedback and data scheduling approaches. The higher-radix FFT algorithm is also realized in our processor to reduce the number of complex multiplications. A test chip for 802.11n system has been designed using 0.13μm 1P8M CMOS process with core area of 2142×660 μm2. Power dissipation is 5.2mW when 128 points FFT with four data streams are calculated.

Original languageEnglish
Title of host publication2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
PublisherIEEE Computer Society
Pages225-228
Number of pages4
ISBN (Print)0780391624, 9780780391628
DOIs
StatePublished - 1 Jan 2005
Event1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005 - Hsinchu, Taiwan
Duration: 1 Nov 20053 Nov 2005

Publication series

Name2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Conference

Conference1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005
CountryTaiwan
CityHsinchu
Period1/11/053/11/05

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