A MPCN-based parallel architecture in BCH decoders for NAND flash memory devices

Yi Min Lin*, Chi Heng Yang, Chih Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

16 Scopus citations

Abstract

According to large-page-size and random-bit-error characteristics, long-block-length Bose-Chaudhuri-Hochquenghem (BCH) decoders are applied to realize error correction in nand Flash memory devices. To accelerate the decoding process in an area-efficient architecture, a parallel architecture with minimal polynomial combinational network (MPCN) for long BCH decoders is presented in this brief. The proposed design utilizes MPCNs to replace constant finite-field multipliers, which dominate the hardware complexity of the high-parallel Chien search architecture. Furthermore, both the syndrome calculator and the Chien search can be merged by exploiting our MPCN-based architecture, leading to significant hardware complexity reduction. From the synthesis results in the 90-nm CMOS technology, the MPCN-based joint syndrome calculation and Chien search has 46.7% gate count saving for parallel-32 BCH (4603, 4096; 39) decoder in contrast with the straightforward design.

Original languageEnglish
Article number6015539
Pages (from-to)682-686
Number of pages5
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume58
Issue number10
DOIs
StatePublished - 1 Oct 2011

Keywords

  • Bose-Chaudhuri-Hochquenghem (BCH) code
  • Chien search
  • error correction code
  • nand Flash memory

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