A monolithic CMOS MEMS accelerometer with chopper correlated double sampling readout circuit

Chun Kai Wang*, Che Sheng Chen, Kuei-Ann Wen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

12 Scopus citations

Abstract

A monolithic CMOS MEMS capacitive accelerometer with micropower analog readout circuit is presented in this paper. In order to optimize noise-power performance of accelerometer in limited area, a specification driven MEMS/IC co-design flow is adopted. In analog readout circuit design, the proposed circuit architecture combines chopper stabilization and correlated double sampling to suppress low frequency noise and compensate DC offset. The RMS input referred noise voltage is 9.82 nV/Hz under 100Hz. The power consumption is 36uW at 100kHz modulation frequency.

Original languageEnglish
Title of host publication2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Pages2023-2026
Number of pages4
DOIs
StatePublished - 2 Aug 2011
Event2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro, Brazil
Duration: 15 May 201118 May 2011

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
CountryBrazil
CityRio de Janeiro
Period15/05/1118/05/11

Fingerprint Dive into the research topics of 'A monolithic CMOS MEMS accelerometer with chopper correlated double sampling readout circuit'. Together they form a unique fingerprint.

Cite this