A mixed analog-digital simulator for ASIC using a novel block tearing approach

Steve S. Chung, J. L. Bie

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A mixed-mode simulator for timing verification of analog-digital CMOS VLSI circuits is reported. It was developed by combining SPICE techniques for analog circuit simulation and gate-level techniques for digital circuit simulation based on the event-driven method. A new scheme called the block tearing (BT) approach at the macrocell level is proposed for memory storage savings while preserving reasonable accuracy. Benchmark tests of several example circuits show good performance in terms of speed and accuracy. The simulator is well suited for hierarchial VLSI circuits which are cell-based, such as current ASIC circuit design.

Original languageEnglish
Title of host publicationProceedings - 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages527-530
Number of pages4
ISBN (Electronic)0780313755, 9780780313750
DOIs
StatePublished - 1 Jan 1993
Event6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993 - Rochester, United States
Duration: 27 Sep 19931 Oct 1993

Publication series

NameProceedings - 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993

Conference

Conference6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993
CountryUnited States
CityRochester
Period27/09/931/10/93

Fingerprint Dive into the research topics of 'A mixed analog-digital simulator for ASIC using a novel block tearing approach'. Together they form a unique fingerprint.

Cite this