A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect

Yong Yu Lin, Fan Ta Chen, Wei-Zen Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A millimeter-wave (mmW) frequency synthesizer for 60GHz wireless transceiver is presented. To achieve wide range and low noise operation, a new sampling PD based PLL (S-PLL) is proposed. In contrast to conventional sub-sampling PD based PLLs, it provides a wider capture range without suffering from harmonic lock problems. Also, compared to conventional CP-based PLLs, the inband noise is improved by 13 dB while the reference spur is improved by more than 16 dB. Implemented in TSMC 28nm CMOS technology, the core circuit occupies a chip area of 0.175mm2. The measured phase noise from a 48 GHz carrier is-95.7dBc/Hz at 1MHz offset. The power consumption is 54mW.

Original languageEnglish
Title of host publication2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Electronic)9781728160832
DOIs
StatePublished - Aug 2020
Event2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020 - Hsinchu, Taiwan
Duration: 10 Aug 202013 Aug 2020

Publication series

Name2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020

Conference

Conference2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
CountryTaiwan
CityHsinchu
Period10/08/2013/08/20

Keywords

  • Charge Pump Phase-locked Loop (CP-PLL)
  • Sampling-PD PLL (S-PLL).
  • Sub-Sampling-PD PLL (SSPLL)

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