A micro-architecture simulator for multimedia stream processor

Fang Ju Lin*, Her-Ming Chiueh

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

Recent research has proposed using stream processors for media applications. Since a programmable Stream Processor could utilize various hardware micro-architectures for diverse media applications, decision on a suitable micro-architectures to achieve efficiencies and hardware cost is critical. In this paper, a micro-architecture simulator for stream processor is implemented. The simulator evaluate the performance of media application executed on various micro-architectures, and then to analyze the utility rate of hardware and consumption of memory. By comparing the performance of media application executed on diverse micro-architectures, the optimized hardware micro-architecture can be determined for specific application and suitable micro-architecture of Stream Processor can be implemented on later VLSI for different targeting systems.

Original languageEnglish
Title of host publicationICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
Pages768-771
Number of pages4
DOIs
StatePublished - 1 Dec 2006
EventICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems - Nice, France
Duration: 10 Dec 200613 Dec 2006

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

ConferenceICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
CountryFrance
CityNice
Period10/12/0613/12/06

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