A methodology with selective pattern compression schemes on reducing test power and test volume

Chia Yi Lin*, Hsiu Chuan Lin, Hung-Ming Chen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

Due to the advancement of modern chip designs, test strategies become one of the most important issues to reduce test costs. In this paper, we proposed a methodology and focus on the large test power dissipation and large test data volume. Our methodology can suppress the test power to avoid chip failures caused by large test power, and the methodology is also effective in reducing the test data volume and shift-in power. The proposed schemes and techniques are based on the selective test pattern compression. They can reduce considerable shift-in power by skipping the switching signal passing through long scan chains. The experimental results with ISCAS89 circuits demonstrate that our methodology can achieve a significant improvement in the reduction of shift-in power and test data volume. Our approach also supports multiple scan chains.

Original languageEnglish
Pages (from-to)75-88
Number of pages14
JournalInternational Journal of Electrical Engineering
Volume17
Issue number1
StatePublished - 1 Feb 2010

Keywords

  • Compression
  • DFT
  • Low power
  • Scan chain
  • Test data volume

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