A memory-efficient deblocking filter for H.264/AVC video coding

Tsu Ming Liu; Wen Ping Lee; Ting An Lin; Chen-Yi Lee

doi:10.1109/ISCAS.2005.1465043

A memory-efficient deblocking filter for H.264/AVC video coding

Tsu Ming Liu^*, Wen Ping Lee, Ting An Lin, Chen-Yi Lee

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to journal › Conference article › peer-review

68 Scopus citations

Abstract

A memory-efficient architecture design for de-blocking filter in H.264/AVC is presented. We use the novel data arrangement of Column-of-Pixel to facilitate the memory access and reuse the pixel value. Further, we propose a hybrid filter scheduling to improve the system throughput. As compared with some existing approaches of realizing de-blocking filter [1] [2], the proposed design saves about one-half of processing cycles. With novel data arrangement and hybrid filter scheduling, an efficient architecture design is implemented. Further, it is evaluated on H.264 system and easily achieved real-time decoding with 1080 HD (1920×1088@30fps) when working frequency is 100MHz.

Original language	English
Article number	1465043
Pages (from-to)	2140-2143
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1465043
State	Published - 1 Dec 2005
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: 23 May 2005 → 26 May 2005

Access to Document

10.1109/ISCAS.2005.1465043

Fingerprint Dive into the research topics of 'A memory-efficient deblocking filter for H.264/AVC video coding'. Together they form a unique fingerprint.

Cite this

@article{5fbea16f662b450ea754544fc8f4f57c,

title = "A memory-efficient deblocking filter for H.264/AVC video coding",

abstract = "A memory-efficient architecture design for de-blocking filter in H.264/AVC is presented. We use the novel data arrangement of Column-of-Pixel to facilitate the memory access and reuse the pixel value. Further, we propose a hybrid filter scheduling to improve the system throughput. As compared with some existing approaches of realizing de-blocking filter [1] [2], the proposed design saves about one-half of processing cycles. With novel data arrangement and hybrid filter scheduling, an efficient architecture design is implemented. Further, it is evaluated on H.264 system and easily achieved real-time decoding with 1080 HD (1920×1088@30fps) when working frequency is 100MHz.",

author = "Liu, {Tsu Ming} and Lee, {Wen Ping} and Lin, {Ting An} and Chen-Yi Lee",

year = "2005",

month = dec,

day = "1",

doi = "10.1109/ISCAS.2005.1465043",

language = "English",

pages = "2140--2143",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "null ; Conference date: 23-05-2005 Through 26-05-2005",

}

TY - JOUR

T1 - A memory-efficient deblocking filter for H.264/AVC video coding

AU - Liu, Tsu Ming

AU - Lee, Wen Ping

AU - Lin, Ting An

AU - Lee, Chen-Yi

PY - 2005/12/1

Y1 - 2005/12/1

N2 - A memory-efficient architecture design for de-blocking filter in H.264/AVC is presented. We use the novel data arrangement of Column-of-Pixel to facilitate the memory access and reuse the pixel value. Further, we propose a hybrid filter scheduling to improve the system throughput. As compared with some existing approaches of realizing de-blocking filter [1] [2], the proposed design saves about one-half of processing cycles. With novel data arrangement and hybrid filter scheduling, an efficient architecture design is implemented. Further, it is evaluated on H.264 system and easily achieved real-time decoding with 1080 HD (1920×1088@30fps) when working frequency is 100MHz.

AB - A memory-efficient architecture design for de-blocking filter in H.264/AVC is presented. We use the novel data arrangement of Column-of-Pixel to facilitate the memory access and reuse the pixel value. Further, we propose a hybrid filter scheduling to improve the system throughput. As compared with some existing approaches of realizing de-blocking filter [1] [2], the proposed design saves about one-half of processing cycles. With novel data arrangement and hybrid filter scheduling, an efficient architecture design is implemented. Further, it is evaluated on H.264 system and easily achieved real-time decoding with 1080 HD (1920×1088@30fps) when working frequency is 100MHz.

UR - http://www.scopus.com/inward/record.url?scp=67649227511&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2005.1465043

DO - 10.1109/ISCAS.2005.1465043

M3 - Conference article

AN - SCOPUS:67649227511

SP - 2140

EP - 2143

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

M1 - 1465043

Y2 - 23 May 2005 through 26 May 2005

ER -

A memory-efficient deblocking filter for H.264/AVC video coding

Abstract

Access to Document

Other files and links

Cite this