A maskable memory architecture for rank-order filtering

Meng Chun Lin*, Lan-Rong Dung

*Corresponding author for this work

Research output: Contribution to conferencePaper

Abstract

This paper presents a novel implementation of rank-order filtering using maskable memory. Based on a bit-serial rank-order filtering algorithm the proposed design uses a special-defined memory,' called parallel maskable memory (PMM) to realize major operations of rank-order filtering, polarization and update. Using the memory-orient architecture, the proposed rank-order filter can benefit from high flexibility, low cost and high speed. PMM has features of bit-sliced read, partial write, and pipelined datapath. Bit-sliced read and partial write are driven by maskable registers. The maskable registers allows PMM to configure operating bits. The bit-sliced read with a polarization selector allows PMM to perform polar determination while the partial write helps next-bit update. Recursively combining the bit-sliced read and partial write, PMM can effectively realizes rank-order filtering in terms of cost and speed.

Original languageEnglish
Pages453-456
Number of pages4
StatePublished - 1 Dec 2004
Event2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
Duration: 6 Dec 20049 Dec 2004

Conference

Conference2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
CountryTaiwan
CityTainan
Period6/12/049/12/04

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  • Cite this

    Lin, M. C., & Dung, L-R. (2004). A maskable memory architecture for rank-order filtering. 453-456. Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.