A low-voltage CMOS LNA design utilizing the technique of capacitive feedback matching network

Chung-Yu Wu*, Fadi Riad Shahroury

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

In this paper, a CMOS low noise amplifier (LNA) with a new input matching topology has been proposed, analyzed, and measured. The input matching network is designed through the technique of capacitive feedback matching network. The proposed LNA which is implemented in a 0.18-μm 1P6M CMOS technology is operated at the frequency of 12.8 GHz. It has a gain S21 of 13.2 dB, a noise figure (NF) of 4.57 dB and an NFmin of 4.46 dB. The reverse isolation S12 of the LNA can achieve -40 dB and the input and output return losses are better than -11 dB. The input 1-dB compression point is -11 dBm. This LNA drains 10 m A from the supply voltage of 1 V.

Original languageEnglish
Title of host publicationICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
Pages78-81
Number of pages4
DOIs
StatePublished - 1 Dec 2006
EventICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems - Nice, France
Duration: 10 Dec 200613 Dec 2006

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

ConferenceICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
CountryFrance
CityNice
Period10/12/0613/12/06

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