A low power pulsed edge-triggered latch for survivor memory unit of Viterbi decoder

Wei Li Su*, Her-Ming Chiueh, Po-Tsang Huang, Wei Hwnag

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A low power pulsed edge-triggered latch based on the static edge-triggered latch (ETL) is presented for survivor memory (SMU) unit of Viterbi decoder for low power high speed wireless local area network (WLAN) applications. By reducing clock loading and transistor number, the proposed low swing static ETL has less clock loading, smaller cell area and power-delay product compared to traditional master-slave register. Moreover, a stage-reduced SMU is introduced later for saving both area and power consumption. The proposed low swing static ETL and stage-reduced SMU are designed and simulated in TSMC 0.13um standard CMOS process, and the operating clock frequency is at 1GHz.

Original languageEnglish
Title of host publicationICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
Pages553-556
Number of pages4
DOIs
StatePublished - 1 Dec 2006
EventICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems - Nice, France
Duration: 10 Dec 200613 Dec 2006

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

ConferenceICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
CountryFrance
CityNice
Period10/12/0613/12/06

Fingerprint Dive into the research topics of 'A low power pulsed edge-triggered latch for survivor memory unit of Viterbi decoder'. Together they form a unique fingerprint.

Cite this