A low power programmable PRBS generator and a clock multiplier unit for 10 Gbps serdes applications

Wei-Zen Chen*, Guan Sheng Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

This paper presents the design of a low power programmable PRBS generator and a low noise clock multiplier unit (CMU) for 10 Gbps serdes applications. The PRBS generator is capable of producing 27-1, 210-1, 215-1, 223-1, and 231-1 b test pattern according to ITU-T recommendations. High speed and low power operations of the PRBS generator are achieved by 16 paths parallel feedback techniques. The measured jitter of the CMU is only 3.56 psrms, and the data jitter at the PRBS output is mainly determined by the CMU. Implemented in a 0.18μm CMOS process, the power dissipation for PRBS generator is only 10.8 mW, and the CMU consumes about 87mW.

Original languageEnglish
Title of host publicationISCAS 2006
Subtitle of host publication2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages3273-3276
Number of pages4
DOIs
StatePublished - 1 Dec 2006
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
Duration: 21 May 200624 May 2006

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

ConferenceISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
CountryGreece
CityKos
Period21/05/0624/05/06

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