A low-power parameterized hardware design for the one-dimensional discrete fourier transform of variable lengths

Jiun-In  Guo*, Chien Chang Lin, Chih Da Chien

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

This paper presents a new low-power parameterized hardware design for the one-dimensional (1D) discrete Fourier transform (DFT) of variable lengths. By combining the cyclic convolution formulation, block-based distributed arithmetic (BDA), and Cooley-Tukey decomposition algorithm together, we have developed a parameterized hardware design for the DFT of variable lengths ranging from 256 to 4096 points and with different modes of performance. The proposed design can perform different lengths of DFT computation through the configuration of parameters, which not only provides the flexibility in computing different length DFT but also facilitates the performance-driven design considerations in terms of power consumption and processing speeds, that is, we can configure the proposed design in different modes of performance by setting different parameters. This feature is beneficial to developing a parameterized DFT soft Intellectual Property (IP) core or hard IP core for meeting the system requirements of different silicon-on-a-chip (SOC) applications as compared with the existing fixed length DFT designs.

Original languageEnglish
Pages (from-to)405-426
Number of pages22
JournalJournal of Circuits, Systems and Computers
Volume11
Issue number4
DOIs
StatePublished - 1 Aug 2002

Keywords

  • Discrete Fourier transform
  • Low power design
  • Parameterized hardware design
  • Silicon IP design
  • SOC design

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