A Low-power motion compensation IP core design for MPEG-1/2/4 video decoding

Chien Chih-Da, Chen Ho-Chun*, Huang Lin-Chieh, Jiun-In Guo

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

7 Scopus citations

Abstract

This paper presents a low-power motion compensation IP core design for the MPEG-1/2/4 video decoding. The proposed design exploits the adder-based quarter-pixel filter optimized by data sharing for low cost consideration. This optimization reduces over 87 % hardware complexity as compared to the quarter-pixel filter in the existing design [4]. In addition, we propose a low-power design technique called dynamic partially guarded computation (DPGC) to reduce the power consumption on the pixel interpolation. After applying the DPGC, we can reduce the 60% power consumption of interpolation operations in the proposed design. Using a 0.18μm CMOS technology, the proposed design achieves real-time processing of MPEG-1/2/4 decoding on 4CIF video when operated at 54MHz. In addition, the proposed design has been integrated into a MPEG-4 video decoder for system verification through XILINX multimedia FPGA board.

Original languageEnglish
Article number1465642
Pages (from-to)4542-4545
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
StatePublished - 1 Dec 2005
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: 23 May 200526 May 2005

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