A low-power low-swing single-ended multi-port SRAM

Hao I. Yang*, Ming Hung Chang, Ssu Yun Lai, Hsiang Fei Wang, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

In this paper, a new single-ended 6-T SRAM cell is proposed. It has a very strong static noise margin (SNM) during read cycles. Meanwhile, data can be easily written because of floating virtual ground and 1-T equalizer insertion within cell. Low-swing writing ability is achieved by these two approaches. A single-ended current-mode sensing amplifier is also presented. This amplifier can sense a very small swing of bitline, equipping with a high noise-rejection and high PVT-tolerance ability. A low-swing 3-port 64×32-bit SRAM macro is simulated in TSMC 130nm CMOS technology. It consumes a minimum of 725μW and 658μW per-port at 1GHz with 1.2V supply voltage for read and write power, respectively.

Original languageEnglish
Title of host publication2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
DOIs
StatePublished - 28 Sep 2007
Event2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu, Taiwan
Duration: 25 Apr 200727 Apr 2007

Publication series

Name2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

Conference

Conference2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
CountryTaiwan
CityHsinchu
Period25/04/0727/04/07

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