This paper presents a power-efficient computing platform for hearing aids. The proposed platform composes four heterogeneous processing elements. Each processing element includes one tiny RISC processor and several power-efficient hardwired accelerators. The hardwired accelerators integrate static floating-point and truncated multiplier to improve signal-to-noise ratio and reduce computational complexity. Compared to the post-truncate multiplication in FIR filter, the proposed static floating-point datapath reduces 50.8% area and improves 2.2 dB SNR simultaneously.
|Number of pages||4|
|State||Published - 28 Sep 2012|
|Event||2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of|
Duration: 20 May 2012 → 23 May 2012
|Conference||2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012|
|Country||Korea, Republic of|
|Period||20/05/12 → 23/05/12|