A low-power H.264/AVC decoder

Ting An Lin*, Tsu Ming Liu, Chen-Yi Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

17 Scopus citations

Abstract

In this paper, we can save memory access in inter and intra prediction by adopting the proposed memory-efficient decoding ordering. In our proposed hierarchical syntax parser, gated clock technique can be effectively applied to reduce power. Simulation shows the proposed design consumes 88mW in real time decoding 1080HD video sequence.

Original languageEnglish
Title of host publication2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Pages283-286
Number of pages4
DOIs
StatePublished - 1 Dec 2005
Event2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) - Hsinchu, Taiwan
Duration: 27 Apr 200529 Apr 2005

Publication series

Name2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Volume2005

Conference

Conference2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
CountryTaiwan
CityHsinchu
Period27/04/0529/04/05

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