This work presents a low-power differential cascode voltage switch with pass gate (DCVSPG) pulsed latch as an edge-triggered flip-flop and, also, implements it in a Viterbi decoder. The proposed DCVSPG pulsed latch is composed of a low-swing pulse generator and a DCVSPG latch. The low- swing pulse generator reduces not only the switching power but the leakage power by stacking gated transistors. The DCVSPG latch captures the input datum in an implicit transparent window that is produced by the low-swing pulse generator. Consistent with the low power consumption and high performance of the DCVSPG circuit technique, the DCVSPG latch can provide an energy-efficient latch. Based on UMC 90 nm CMOS technology, the simulation results reveal that the proposed approach achieves a higher energy efficiency compared to other flip-flops. For the Viterbi decoder, the proposed DCVSPG pulsed latch can reduce power consumption by 22.2% from that of the C2 MOS flip-flop obtained from the UMC 90 nm low-power cell library.
- Pulsed Latch
- Viterbi Decoder