A low-power design for Reed-Solomon decoders

Hsie-Chia Chang; Chen-Yi Lee

doi:10.1142/S0218126603000726

A low-power design for Reed-Solomon decoders

Hsie-Chia Chang^*, Chen-Yi Lee

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

In this paper, a low-power design for the Reed-Solomon (RS) decoder is presented. Our approach includes a novel two-stage syndrome calculator that reduces the syndrome computations by one-half, a modified Berlekamp-Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The test chip for (255, 239) and (208, 192) RS decoders are implemented by 0.25 μm CMOS 1P5M and 0.35 μm CMOS SPQM standard cells, respectively. Simulation results show our approach can work successfully and achieved large reduction of power consumption on the average.

Original language	English
Pages (from-to)	159-170
Number of pages	12
Journal	Journal of Circuits, Systems and Computers
Volume	12
Issue number	2
DOIs	https://doi.org/10.1142/S0218126603000726
State	Published - 1 Apr 2003

Keywords

Berlekamp-Massey algorithm
Euclidean algorithm
Low-power design
Reed-Soloman codes
Two-stage syndrome calculator

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10.1142/S0218126603000726

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AB - In this paper, a low-power design for the Reed-Solomon (RS) decoder is presented. Our approach includes a novel two-stage syndrome calculator that reduces the syndrome computations by one-half, a modified Berlekamp-Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The test chip for (255, 239) and (208, 192) RS decoders are implemented by 0.25 μm CMOS 1P5M and 0.35 μm CMOS SPQM standard cells, respectively. Simulation results show our approach can work successfully and achieved large reduction of power consumption on the average.

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