A low-power DCO using interlaced hysteresis delay cells

Chien Ying Yu*, Ching Che Chung, Chia Jung Yu, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

25 Scopus citations

Abstract

This brief presents a low-power small-area digitally controlled oscillator (DCO). The coarse-fine architecture with binary-weighted delay stages is applied for the delay range and resolution optimization. The coarse-tuning stage of the DCO uses the interlaced hysteresis delay cell, which is power and area efficient, as compared with conventional delay cells. The glitch protection synchronous circuit makes the DCO easily controllable without generating glitches. A demonstrative all-digital phase-locked loop using the DCO is fabricated in a 90-nm CMOS process with an active area of 0.0086 mm 2. The measured output frequency range is 180-530 MHz at the supply of 1 V. The power consumption are 466 and 357 μW at 480-and 200-MHz output, respectively.

Original languageEnglish
Article number6298003
Pages (from-to)673-677
Number of pages5
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume59
Issue number10
DOIs
StatePublished - 18 Sep 2012

Keywords

  • All-digital phase-locked loop (ADPLL)
  • digitally controlled oscillator (DCO)
  • interlaced hysteresis delay cell (IHDC)
  • low power

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