A low-power crossroad switch architecture and its core placement for network-on-chip

Kuei Chung Chang*, Jih Sheng Shen, Tien-Fu Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the SoCs will be heterogeneous in nature with widely varying functionality and communication requirements. The communication topology should possibly match communication workflows among these components. In this paper, we first propose an interconnection architecture for SoC, which uses crossroad switches to construct a dedicated communication path dynamically between any two cores. We then present a design methodology for constructing network on chip (NoC) for application-specific computer systems with profiled communication characteristics. We design a core placement tool, which automatically maps cores to a communication topology such that we can minimize the total communication energy. Experimental results show that the design methodology can generate optimized on-chip networks with fewer resources than meshes and tori, and the power saving approximates to 40%.

Original languageEnglish
Title of host publicationISLPED '05: PROCEEDINGS OF THE 2005 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN
PublisherACM
Pages375-380
Number of pages6
ISBN (Print)1-59593-137-6
DOIs
StatePublished - 12 Dec 2005
Event2005 International Symposium on Low Power Electronics and Design - San Diego, CA, United States
Duration: 8 Aug 200510 Aug 2005

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Conference

Conference2005 International Symposium on Low Power Electronics and Design
CountryUnited States
CitySan Diego, CA
Period8/08/0510/08/05

Keywords

  • Application-specific
  • Low-Power
  • Networks On Chip
  • Systems On Chips

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