A synchronous pulsed signaling system using on-chip capacitive coupling for low-power high-speed buses has been implemented in a 0.10-μm CMOS DRAM process. We demonstrate 1.0-Gb/s/pair differential pulsed signaling over 10-cm PCB lines with an increased channel 3-dB bandwidth of 2.94GHz by blocking the driver/receiver capacitances on a bus and eliminating ESD structures. The system dissipates 1.92mW for both the driver and channel termination at 500MHz and 1.8-V supply, which is only 1/8 to 1/13 of conventional memory buses using SSTL-2 and RSL.
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - 1 Dec 2004|
|Event||Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC - Orlando, FL, United States|
Duration: 3 Oct 2004 → 6 Oct 2004