A low power and memory efficient distributed arithmetic design and its DCT application

Hun Chen Chen*, Tian-Sheuan Chang, Chein Wei Jen

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations

Abstract

This paper presents a low power Distributed Arithmetic (DA) realization of cyclic convolution and its application to discrete cosine transform (DCT). We exploit DA technique, and the redundancy appeared in the rotated input data of cyclic convolution to realize the cyclic convolution by using the scheme of address morphing that converts the distribution of DA input address into a subset of it with minimal transition probability such that the memory size and transition activity in the DA design can be minimized to achieve memory efficient as well as low power consumption. Regarding the DCT design, we exploit the symmetry property of DCT coefficients to reformulate the 1-D DCT to two smaller perfect cyclic forms with difference and sum of the input samples, and then apply the proposed DA design to facilitate an efficient realization of 1-D DCT. Furthermore, according to the property of signal correlation, we combine the MSB rejection technique with the proposed GDA design to further reduce the cycles of DA computation for the DCT outputs with the difference of input samples. As shown in the simulation result, the design with the proposed approach facilitates not only reducing the memory size, but also improving the power consumption significantly than the conventional one.

Original languageEnglish
Pages805-808
Number of pages4
StatePublished - 1 Dec 2004
Event2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
Duration: 6 Dec 20049 Dec 2004

Conference

Conference2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
CountryTaiwan
CityTainan
Period6/12/049/12/04

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