This paper presents a 166Mb/s, 64-state, radix-4, 16-level soft decision Viterbi decoder for high speed WLAN applications. With the path merging and trace forward techniques, the memory read operations are reduced to save power consumption. A test chip is fabricated in 0.35μm IP4M CMOS process, and can achieve the maximum throughput rate of 166Mbit/s under 3.3V. The measured power consumption is below 55mW under 166Mb/s throughput rate at 2.2V.
|Number of pages||4|
|Journal||European Solid-State Circuits Conference|
|State||Published - 1 Dec 2003|
|Event||29th European Solid-State Circuits Conference, ESSCIRC 2003 - Estoril, Portugal|
Duration: 16 Sep 2003 → 18 Sep 2003