A low power 2.4/5.2GHz concurrent receiver using current-reused architecture

Hung Sheng Hsu, Qiu Yue Duan, Yu-Te Liao

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

This paper presents a low-power 2.4/5.2GHz concurrent receiver for emerging wireless sensing applications. The RF front-end design includes a concurrent dual-band low noise amplifier (LNA), a stacked mixer and VCO architecture, and variable-gain baseband amplifiers (VGA). Current-reused techniques, by sharing gain stages and stacked components, are explored in the receiver design for the further reduction of power consumption. The prototype chip, which was fabricated in a 0.18μm CMOS process, occupies a chip area of 3.67mm2, including pads and impedance matching networks. At the 2.4GHz band, the proposed receiver achieves a maximum gain of 43dB, a noise figure of 8.9dB, and a 1-dB compression point (P1dB) larger than -34dBm. At the 5.2GHz band, the proposed receiver achieves a maximum gain of 31dB, a noise figure of 16.3dB, and a P1dB larger than -27dBm. The total power consumption is 7.3mW at a supply voltage of 1.2V.

Original languageEnglish
Title of host publicationISCAS 2016 - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1398-1401
Number of pages4
ISBN (Electronic)9781479953400
DOIs
StatePublished - 29 Jul 2016
Event2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada
Duration: 22 May 201625 May 2016

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2016-July
ISSN (Print)0271-4310

Conference

Conference2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
CountryCanada
CityMontreal
Period22/05/1625/05/16

Keywords

  • CMOS
  • current-reused
  • dual-band
  • low power

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