A low latency memory controller for video coding systems

Chih Da Chien*, Chih Wei Wang, Chiun Chau Lin, Tien Wei Hsieh, Yuan Hwa Chu, Jiun-In  Guo

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

The dynamic memory controller plays an important role in system-on-a-chip (SoC) designs to provide enough memory bandwidth through external memory for DSP and multimedia processing. However, the overhead cycles in accessing the data located in external memory have much influence on the SoC performance. In this paper, we propose a low latency memory controller with AHB interface to reduce the overhead cycles for the SDR memory access in the SoC designs. Through the pre-calculated addresses of impending transfers, two memory control schemes, i.e. Burst terminates Burst (BTB) and Anticipative Row Activation (ARA), are used to reduce the latency of SDR memory access. The experimental results show that the proposed memory controller reduces the memory bandwidth by 33% in a typical MPEG-4 video decoding system.

Original languageEnglish
Title of host publicationProceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007
Pages1211-1214
Number of pages4
DOIs
StatePublished - 1 Dec 2007
EventIEEE International Conference onMultimedia and Expo, ICME 2007 - Beijing, China
Duration: 2 Jul 20075 Jul 2007

Publication series

NameProceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007

Conference

ConferenceIEEE International Conference onMultimedia and Expo, ICME 2007
CountryChina
CityBeijing
Period2/07/075/07/07

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