This paper proposes a low-cost output response analyzer (ORA) for the built-in-self-test (BIST) σ-Δ ADC based on the controlled sine wave fitting (CSWF) method. The ADC under test (AUT) is composed of a design-for-digital-testability (DfDT) second-order σ-Δ modulator and a decimation filter. The CSWF BIST procedure requests an ORA to accept the output of the AUT and calculates the offset, the amplitude of the stimulus tone response, and the total-harmonic-distortion-and noise (THD+N) power in three successive BIST steps respectively. Each BIST step needs an accumulator to conduct the specified BIST function. By sharing an accumulator for every BIST step, the proposed ORA design contains only 1.9k gates without loss of computational accuracy. The hardware is only 34% of the original design. Simulation results show that the proposed ORA presents accurate SNDR results for the 1 kHz tests.