A low-cost output response analyzer for the built-in-self-test σ-Δ modulator based on the controlled sine wave fitting method

Shao Feng Hung*, Hao-Chiao Hong, Sheng Chuan Liang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

This paper proposes a low-cost output response analyzer (ORA) for the built-in-self-test (BIST) σ-Δ ADC based on the controlled sine wave fitting (CSWF) method. The ADC under test (AUT) is composed of a design-for-digital-testability (DfDT) second-order σ-Δ modulator and a decimation filter. The CSWF BIST procedure requests an ORA to accept the output of the AUT and calculates the offset, the amplitude of the stimulus tone response, and the total-harmonic-distortion-and noise (THD+N) power in three successive BIST steps respectively. Each BIST step needs an accumulator to conduct the specified BIST function. By sharing an accumulator for every BIST step, the proposed ORA design contains only 1.9k gates without loss of computational accuracy. The hardware is only 34% of the original design. Simulation results show that the proposed ORA presents accurate SNDR results for the 1 kHz tests.

Original languageEnglish
Title of host publicationProceedings of the 18th Asian Test Symposium, ATS 2009
Pages385-388
Number of pages4
DOIs
StatePublished - 1 Dec 2009
Event18th Asian Test Symposium, ATS 2009 - Taichung, Taiwan
Duration: 23 Nov 200926 Nov 2009

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Conference

Conference18th Asian Test Symposium, ATS 2009
CountryTaiwan
CityTaichung
Period23/11/0926/11/09

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