FFT-based OFDM and SC-FDMA transmission technologies have been widely adopted in most advanced telecommunication systems. For future 5G mobile communication systems, FFT again is expected to play very crucial roles. As such, design of FFT processors with unprecedentedly high performance has become a hard challenging problem that must be overcome. Among the components of an FFT processor, the rotator composed of ROMs and multipliers for twiddle factor multiplications take up the most area and power consumption. In order to reduce the cost, a reconfigurable multiplier-less and ROM-less rotator design approach is proposed in this paper. This approach supports both power-of-Two and non-power-of-Two FFT lengths. It effectively reduces the area by applying a series of decomposition and sharing schemes. An example of a rotator supporting 128-2048/1536-point FFT processor for the 4G LTE system is implemented with TSMC 90nm CMOS technology. Compared to the existing design, this work has 16.75% area reduction and 62.94% power reduction.