A long block length BCH decoder for DVB-S2 application

Yi Min Lin*, Jau Yet Wu, Chien Ching Lin, Hsie-Chia Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

In this paper, a low-complexity and full-mode BCH decoder with long block length for DVB-S2 application is presented. With the reversed error locator polynomial, our proposed reversed Berlekamp-Massey algorithm features a sharing architecture to perform parallel-4 syndrome and Chien search calculations. Concatenated with the LDPC decoder, which has a long decoding latency and a short period of data output time, the proposed parallel-4 BCH decoder ensures the sufficient throughput with only one bank memory. Moreover, a composite field divider instead of a large Galois field inversion table is also presented to reduce complexity. After implemented in 0.13μ m CMOS technology, our parallel-4 BCH decoder occupied 44K gate count can reach 380Mb/s according to the post-layout simulations.

Original languageEnglish
Title of host publicationISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings
Pages171-174
Number of pages4
StatePublished - 1 Dec 2009
Event12th International Symposium on Integrated Circuits, ISIC-2009 - Singapore, Singapore
Duration: 14 Dec 200916 Dec 2009

Publication series

NameISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings

Conference

Conference12th International Symposium on Integrated Circuits, ISIC-2009
CountrySingapore
CitySingapore
Period14/12/0916/12/09

Fingerprint Dive into the research topics of 'A long block length BCH decoder for DVB-S2 application'. Together they form a unique fingerprint.

Cite this