A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme

Wei Hsin Chang; Yew San Lee; Wen-Shiaw Peng; Chen-Yi Lee

doi:10.1109/ISCAS.2001.922239

A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme

Wei Hsin Chang, Yew San Lee, Wen-Shiaw Peng, Chen-Yi Lee

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

38 Scopus citations

Abstract

In this paper, we present a memory efficient VLSI architecture for 2-D Discrete Wavelet Transform (DWT) using lifting scheme. The advantages of lifting scheme are lower computational complexity, transforming signal without extension and reduced memory requirement. It decomposes the wavelet transform with finite taps into two coefficient sets named predictor and updater. Base on the lifting scheme, we explore its data dependency of input and output signals, and thus propose a programmable architecture for different filter banks with low memory usage. For the computation of NxN 2-D DWT with Daubechies 9-7 filter, our architecture requires 9N storage cells and the memory bandwidth requirement is almost one-half of JPEG2000's proposal. This architecture is suitable for VLSI implementation and various real-time image/video applications.

Original language	English
Title of host publication	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages	330-333
Number of pages	4
Volume	626
DOIs	https://doi.org/10.1109/ISCAS.2001.922239
State	Published - 1 Dec 2001
Event	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia Duration: 6 May 2001 → 9 May 2001

Publication series

Name	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume	4

Conference

Conference	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Country	Australia
City	Sydney, NSW
Period	6/05/01 → 9/05/01

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10.1109/ISCAS.2001.922239

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Chang, W. H., Lee, Y. S., Peng, W-S., & Lee, C-Y. (2001). A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings (Vol. 626, pp. 330-333). [922239] (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 4). https://doi.org/10.1109/ISCAS.2001.922239

Chang, Wei Hsin ; Lee, Yew San ; Peng, Wen-Shiaw ; Lee, Chen-Yi. / A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme. ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. Vol. 626 2001. pp. 330-333 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings).

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abstract = "In this paper, we present a memory efficient VLSI architecture for 2-D Discrete Wavelet Transform (DWT) using lifting scheme. The advantages of lifting scheme are lower computational complexity, transforming signal without extension and reduced memory requirement. It decomposes the wavelet transform with finite taps into two coefficient sets named predictor and updater. Base on the lifting scheme, we explore its data dependency of input and output signals, and thus propose a programmable architecture for different filter banks with low memory usage. For the computation of NxN 2-D DWT with Daubechies 9-7 filter, our architecture requires 9N storage cells and the memory bandwidth requirement is almost one-half of JPEG2000's proposal. This architecture is suitable for VLSI implementation and various real-time image/video applications.",

author = "Chang, {Wei Hsin} and Lee, {Yew San} and Wen-Shiaw Peng and Chen-Yi Lee",

year = "2001",

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Chang, WH, Lee, YS, Peng, W-S & Lee, C-Y 2001, A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme. in ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. vol. 626, 922239, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings, vol. 4, pp. 330-333, 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, NSW, Australia, 6/05/01. https://doi.org/10.1109/ISCAS.2001.922239

A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme. / Chang, Wei Hsin; Lee, Yew San; Peng, Wen-Shiaw; Lee, Chen-Yi.

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. Vol. 626 2001. p. 330-333 922239 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 4).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - In this paper, we present a memory efficient VLSI architecture for 2-D Discrete Wavelet Transform (DWT) using lifting scheme. The advantages of lifting scheme are lower computational complexity, transforming signal without extension and reduced memory requirement. It decomposes the wavelet transform with finite taps into two coefficient sets named predictor and updater. Base on the lifting scheme, we explore its data dependency of input and output signals, and thus propose a programmable architecture for different filter banks with low memory usage. For the computation of NxN 2-D DWT with Daubechies 9-7 filter, our architecture requires 9N storage cells and the memory bandwidth requirement is almost one-half of JPEG2000's proposal. This architecture is suitable for VLSI implementation and various real-time image/video applications.

AB - In this paper, we present a memory efficient VLSI architecture for 2-D Discrete Wavelet Transform (DWT) using lifting scheme. The advantages of lifting scheme are lower computational complexity, transforming signal without extension and reduced memory requirement. It decomposes the wavelet transform with finite taps into two coefficient sets named predictor and updater. Base on the lifting scheme, we explore its data dependency of input and output signals, and thus propose a programmable architecture for different filter banks with low memory usage. For the computation of NxN 2-D DWT with Daubechies 9-7 filter, our architecture requires 9N storage cells and the memory bandwidth requirement is almost one-half of JPEG2000's proposal. This architecture is suitable for VLSI implementation and various real-time image/video applications.

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Chang WH, Lee YS, Peng W-S, Lee C-Y. A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. Vol. 626. 2001. p. 330-333. 922239. (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings). https://doi.org/10.1109/ISCAS.2001.922239

A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme

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