A lightweight 1.16 pJ/bit processor for the authenticated encryption scheme KetjeSR

Yun Wen Lu, Antoon Purnal, Simon Vandenhende, Chen Yi Lee, Ingrid Verbauwhede, Hsie Chia Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents the results of the first ASIC implementation of the authenticated encryption scheme KetjeSR. The design covers the encryption and decryption operation in combination with a handshake protocol for the data transfer. The chip implementation was done in a TSMC 90nm GUTM process. The encryption/decryption module has an area footprint of 12.2kGE. The processor reaches an end-to-end throughput of 2.08 Gbps when running at a clock frequency of 130 MHz. The design was further optimized for low power and consumes 2.421 mW. The optimization is based on the reuse of the permutation function in combination with extensive pipelining. In terms of energy, the encryption operation costs 1.16 pJ/bit.

Original languageEnglish
Title of host publication2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728106557
DOIs
StatePublished - Apr 2019
Event2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan
Duration: 22 Apr 201925 Apr 2019

Publication series

Name2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Conference

Conference2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
CountryTaiwan
CityHsinchu
Period22/04/1925/04/19

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    Lu, Y. W., Purnal, A., Vandenhende, S., Lee, C. Y., Verbauwhede, I., & Chang, H. C. (2019). A lightweight 1.16 pJ/bit processor for the authenticated encryption scheme KetjeSR. In 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 [8741601] (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2019.8741601