The ever-increasing transistor threshold-voltage (Vth) variation caused by process technologies shrink brings the performance and reliability issues in SRAM cells. To keep power limitations, scaling down the supply voltage is inevitable in mobile devices and future chips. However, caches become susceptible even fail in low voltages, and the distribution of access latencies increases in new technology nodes. To deal with the respectable power of SRAM in modern processors, the memory reliability wall poses a major challenge in cache design nowadays and continues for years to come. This thesis proposes a latency-elastic and fault-tolerant cache not only for fault-tolerant, but aiming at the performance issues. It varies the latency of cache access to achieve better-than-worst-case designs for improving performance.