A latency-elastic and fault-tolerant cache for improving performance and reliability on low voltage operation

Yung Hui Yu, Po Hao Wang, Shang Jen Tsai, Tien-Fu Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

The ever-increasing transistor threshold-voltage (Vth) variation caused by process technologies shrink brings the performance and reliability issues in SRAM cells. To keep power limitations, scaling down the supply voltage is inevitable in mobile devices and future chips. However, caches become susceptible even fail in low voltages, and the distribution of access latencies increases in new technology nodes. To deal with the respectable power of SRAM in modern processors, the memory reliability wall poses a major challenge in cache design nowadays and continues for years to come. This thesis proposes a latency-elastic and fault-tolerant cache not only for fault-tolerant, but aiming at the performance issues. It varies the latency of cache access to achieve better-than-worst-case designs for improving performance.

Original languageEnglish
Title of host publication2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479962754
DOIs
StatePublished - 28 May 2015
Event2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan
Duration: 27 Apr 201529 Apr 2015

Publication series

Name2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Conference

Conference2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
CountryTaiwan
CityHsinchu
Period27/04/1529/04/15

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