A Java processor IP design for embedded SoC

Chun-Jen Tsai, H. W. Kuo, Z. Lin, Z. J. Guo, J. F. Wang

Research output: Contribution to journalArticlepeer-review

5 Scopus citations


In this article, we present a reusable Java processor IP for application processors of embedded systems. For the Java microarchitecture, we propose a low-cost stack memory design that supports a two-fold instruction folding pipeline and a low-complexity Java exception handling hardware.We also propose a mapping between the Java dynamic class loading model and the SoC platform-based design principle so that the Java core can be encapsulated as a reusable IP. To achieve this goal, a two-level method area with two on-chip circular buffers is proposed as an interface between the RISC core and the Java core. The proposed architecture is implemented on a Xilinx Virtex-5 FPGA device. Experimental results show that its performance has some advantages over other Java processors and a Java VM with JIT acceleration on a PowerPC platform.

Original languageEnglish
Number of pages1
JournalACM Transactions on Embedded Computing Systems
Issue number2
StatePublished - 1 Feb 2015


  • Application processor soc
  • Dynamic class loading
  • Embedded systems
  • Java accelerator

Fingerprint Dive into the research topics of 'A Java processor IP design for embedded SoC'. Together they form a unique fingerprint.

Cite this