A highly efficient vlsi architecture for H.264/AVC level 5.1 CABAC decoder

Yuan Hsin Liao*, Gwo Long Li, Tian-Sheuan Chang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

14 Scopus citations

Abstract

In this paper, a high throughput context-based adaptive binary arithmetic coding decoder design is proposed. This decoder employs a syntax element prediction method to solve pipeline hazard problems. It also uses a new hybrid memory two-symbol parallel decoding in order to enhance performance as well as to reduce costs. The critical path delay of the two-symbol binary arithmetic decoding engine is improved by 28% with an efficient mathematical transform. Experimental results show that the throughput of our proposed design can reach 485.76 Mbins/s in the high bit-rate coding and 446.2 Mbins/s on average at 264MHz operating frequency, which is sufficient to support H.264/AVC level 5.1 real-time decoding.

Original languageEnglish
Article number5934379
Pages (from-to)272-281
Number of pages10
JournalIEEE Transactions on Circuits and Systems for Video Technology
Volume22
Issue number2
DOIs
StatePublished - 1 Feb 2012

Keywords

  • Binary arithmetic coding
  • CABAC
  • entropy decoding
  • H.264/AVC
  • syntax parsing

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