A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process

Zhicong Luo, Ming-Dou Ker

Research output: Contribution to journalArticlepeer-review

14 Scopus citations

Abstract

This paper presents a 4 × VDD neuro-stimulator in a 0.18-μm 1.8 V/3.3 V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent transistors from the electrical overstress and gate-oxide reliability issue. A high-voltage-tolerant level shifter with power-on protection is used to drive the neuro-stimulator The reliability measurement of up to 100 million periodic cycles with 3000-μA biphasic stimulations in 12-V power supply has verified that the proposed neuro-stimulator is robust. Precise charge balance is achieved by using a novel current memory cell with the dual calibration loops and leakage current compensation. The charge mismatch is down to 0.25% over all the stimulus current ranges (200-300 μA) The residual average dc current is less than 6.6 nA after shorting operation.

Original languageEnglish
Article number7440898
Pages (from-to)1087-1099
Number of pages13
JournalIEEE Transactions on Biomedical Circuits and Systems
Volume10
Issue number6
DOIs
StatePublished - 1 Dec 2016

Keywords

  • Charge balance
  • current memory cell
  • high-voltage-tolerant
  • leakage current compensation
  • level shifter
  • Stimulator

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