A high-troughput radix-4 log-MAP decoder with low complexity LLR architecture

Hsiang Tsung Chuang*, Kai Hsin Tseng, Wai-Chi  Fang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

The throughput of turbo decoder is limited by the recursion architecture. In this paper, an improved radix-4 recursion architecture is presented. In order to decrease the critical path delay, a hybrid 4-inputs addition/subtraction structure is employed. Moreover, we present a modified trace-back architecture to decrease the hardware complexity of the log-likelihood ratios (LLR) architecture. The area of the proposed MAP decoder is 0.58 mm2 on UMC 0.13μm standard cell technology and under the worst case a maximum throughput of 600 Mbps can be achieved.

Original languageEnglish
Title of host publication2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Pages231-234
Number of pages4
DOIs
StatePublished - 1 Dec 2009
Event2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
Duration: 28 Apr 200930 Apr 2009

Publication series

Name2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Conference

Conference2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
CountryTaiwan
CityHsinchu
Period28/04/0930/04/09

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