A high-throughput radix-16 FFT processor with parallel and normal input/output ordering for IEEE 802.15.3c systems

Shen Jui Huang*, Sau-Gee Chen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

48 Scopus citations

Abstract

This paper presents a high-throughput FFT processor for IEEE 802.15.3c (WPANs) standard. To meet the throughput requirement of 2.59 Giga-samples/s, radix-16 FFT algorithm is adopted and reformulated to an efficient form so that the required number of butterfly stages is reduced. Specifically, the radix-16 butterfly processing element consists of two cascaded parallel/pipelined radix-4 butterfly units. It facilitates low-complexity realization of radix-16 butterfly operation and high operation speed due to its optimized pipelined structure. Besides, a new three-stage multiplier for twiddle factor multiplication is also proposed, which has lower area and power consumption than conventional complex multipliers. Moreover, a conflict-free multibank memory addressing scheme is devised to support up to 16-way parallel and normal-order data input/output. Without needing to reorder the input/output data, this scheme helps a high-throughput design result. Equipped with those new performance-boosting techniques, overall the proposed radix-16 FFT processor is area-efficient with high data processing rate and hardware utilization efficiency. The EDA synthesis results show that whole FFT processor area is 0.93 mm 2, and the power consumption is 42 mW with 90 nm process. The SQNR performance is 57 dB with 12-bit wordlength implementation.

Original languageEnglish
Article number6127888
Pages (from-to)1752-1765
Number of pages14
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume59
Issue number8
DOIs
StatePublished - 16 Jan 2012

Keywords

  • Fast Fourier transform (FFT)
  • non-conflict memory addressing scheme
  • OFDM
  • radix-16 FFT
  • WPANs

Fingerprint Dive into the research topics of 'A high-throughput radix-16 FFT processor with parallel and normal input/output ordering for IEEE 802.15.3c systems'. Together they form a unique fingerprint.

Cite this