For next generation image compression standard, context-based arithmetic coding is adopted for improving compression rate. Efficient and high throughput codec design is strongly required for handling high-resolution images. We propose an efficient codec architecture for context-based adaptive arithmetic coding, which exhibits low cost, low latency, and high throughput rate. In addition, it can be programmed for supporting multiple standards such as JPEG, JPEG2000, JBIG, and JBIG2 standards. It is exploiting three-pipeline stages architecture. Based on parallel leading zeros detection and bit-stuffing handling, symbol can be encoded and decoded within one cycle. Therefore, throughput rate can be increased as high as codec operating clock rate. For 0.35u 1P4M CMOS technology, both encoding and decoding rate can run up to 185Msymbol/sec. The AC codec only costs 12K gate count and 860um × 860um layout area. These performances can meet high-resolution real time application requirement.
|State||Published - 1 Jan 2002|
|Event||International Conference on Image Processing (ICIP'02) - Rochester, NY, United States|
Duration: 22 Sep 2002 → 25 Sep 2002
|Conference||International Conference on Image Processing (ICIP'02)|
|Period||22/09/02 → 25/09/02|