A high throughput CAVLC design for HEVC

Hsuan Ku Chen*, Tian-Sheuan Chang

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

This paper proposes a high throughput context adaptive variable length coding (CAVLC) hardware design for high bit rate HEVC standard. The proposed design adopts a multi-coefficient encoding architecture with the input-parallel information-cascade method to solve the data dependency while attain high throughput. The final implementation with 90nm CMOS technology can process at least 3.2 coefficients per cycle with 12193 gate count when operate at 270MHz. This processing rate can support real video coding with 4Kx2K@60fps at the high bit rate case.

Original languageEnglish
Pages1919-1922
Number of pages4
DOIs
StatePublished - 28 Sep 2012
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 20 May 201223 May 2012

Conference

Conference2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
CountryKorea, Republic of
CitySeoul
Period20/05/1223/05/12

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