This paper proposes a high throughput context adaptive variable length coding (CAVLC) hardware design for high bit rate HEVC standard. The proposed design adopts a multi-coefficient encoding architecture with the input-parallel information-cascade method to solve the data dependency while attain high throughput. The final implementation with 90nm CMOS technology can process at least 3.2 coefficients per cycle with 12193 gate count when operate at 270MHz. This processing rate can support real video coding with 4Kx2K@60fps at the high bit rate case.
|Number of pages||4|
|State||Published - 28 Sep 2012|
|Event||2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of|
Duration: 20 May 2012 → 23 May 2012
|Conference||2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012|
|Country||Korea, Republic of|
|Period||20/05/12 → 23/05/12|