A high-throughput and area-efficient video transform core with a time division strategy

Yuan Ho Chen*, Ruei Yuan Jou, Tsin Yuan Chang, Chih Wen Lu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

In this paper, a 2-D forward discrete cosine transform (FDCT) and inverse DCT (IDCT) core are presented. The proposed DCT core uses a single 1-D transform core and a transpose memory in order to achieve an area-efficient design. By exploiting the even and odd symmetrical properties of the FDCT and IDCT computations, the DCT core can share hardware resources. Furthermore, first-dimensional (1st-D) and second-dimensional (2nd-D) operations can be run simultaneously (1st-D FDCT, 2nd-D FDCT, 1st-D IDCT, 2nd-D IDCT) in the proposed 1-D core by using the proposed time division strategy, which shares hardware resources achieving a high-throughput design. Measurement results show that the DCT core achieves a throughput of 250 MP/s when simultaneously operating FDCT and IDCT, consuming only 19650 logic gates when fabricated using the TSMC 0.18-μ m} CMOS process. The DCT core achieves superior hardware efficiency compared to the existing cores.

Original languageEnglish
Article number6674066
Pages (from-to)2268-2277
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume22
Issue number11
DOIs
StatePublished - 1 Nov 2014

Keywords

  • Area efficiency
  • forward and inverse discrete cosine transform
  • high throughput
  • time division strategy.

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