A high-speed/low-power multiplier using an advanced spurious power suppression technique

Kuan Hung Chen*, Yuan Sun Chu, Yu Min Chen, Jiun-In  Guo

*Corresponding author for this work

Research output: Contribution to journalConference article

1 Scopus citations

Abstract

This study provides the experience of applying an advanced version of our former Spurious Power Suppression Technique (SPST) on multipliers for high-speed and low-power purposes. To filter out the useless switching power, there are two approaches, i.e. using registers and using AND gates, to assert the data signals of multipliers after the data transition. The simulation results show that the SPST implementation with AND gates owns an extremely high flexibility on adjusting the data asserting time which not only facilitates the robustness of SPST but also leads to a 40% speed improvement. By adopting a 0.18-μm CMOS technology, the proposed SPST-equipped multiplier dissipates only 0.0121 mW per MHz in H.264 texture coding applications, and obtains a 40% power reduction.

Original languageEnglish
Article number4253344
Pages (from-to)3139-3142
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
StatePublished - 27 Sep 2007
Event2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
Duration: 27 May 200730 May 2007

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