A high-speed HBT prescaler based on the divideby-two topology

Hung Ju Wei; Chin-Chun Meng; Yu Wen Chang; Yi Chen Lin; Guo Wei Huang

doi:10.1109/APMC.2007.4554716

A high-speed HBT prescaler based on the divideby-two topology

Hung Ju Wei^*, Chin-Chun Meng, Yu Wen Chang, Yi Chen Lin, Guo Wei Huang

^*Corresponding author for this work

National Chiao Tung University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper demonstrates the Divide-by-4/5 prescalers with merged AND gates in 2 μm GaInP/GaAs heterojunction bipolar transistor (HBT) and 0.35 μm SiGe HBT technologies. By biasing the HBT near the peak transit-time frequency (f_T), the maximum operating frequency of a D-type flip-flop (D-FF) can be promoted. At the supply voltage of 5 V, the GaInP/GaAs prescaler operates from 30 MHz to 5.2 GHz, and the SiGe prescaler has the higher-speed performance of 1 GHz ∼ 8 GHz at the cost of power consumption.

Original language	English
Title of host publication	2007 Asia-Pacific Microwave Conference, APMC
DOIs	https://doi.org/10.1109/APMC.2007.4554716
State	Published - 1 Dec 2007
Event	Asia-Pacific Microwave Conference, APMC 2007 - Bangkok, Thailand Duration: 11 Dec 2007 → 14 Dec 2007

Publication series

Name	Asia-Pacific Microwave Conference Proceedings, APMC

Conference

Conference	Asia-Pacific Microwave Conference, APMC 2007
Country	Thailand
City	Bangkok
Period	11/12/07 → 14/12/07

Keywords

Divide-by-4/5
Dual-modulus
Emitter couple logic (ECL)
GaInP/GaAs HBT
Prescaler
SiGe HBT

Access to Document

10.1109/APMC.2007.4554716

Link to publication in Scopus

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Cite this

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title = "A high-speed HBT prescaler based on the divideby-two topology",

abstract = "This paper demonstrates the Divide-by-4/5 prescalers with merged AND gates in 2 μm GaInP/GaAs heterojunction bipolar transistor (HBT) and 0.35 μm SiGe HBT technologies. By biasing the HBT near the peak transit-time frequency (fT), the maximum operating frequency of a D-type flip-flop (D-FF) can be promoted. At the supply voltage of 5 V, the GaInP/GaAs prescaler operates from 30 MHz to 5.2 GHz, and the SiGe prescaler has the higher-speed performance of 1 GHz ∼ 8 GHz at the cost of power consumption.",

keywords = "Divide-by-4/5, Dual-modulus, Emitter couple logic (ECL), GaInP/GaAs HBT, Prescaler, SiGe HBT",

author = "Wei, {Hung Ju} and Chin-Chun Meng and Chang, {Yu Wen} and Lin, {Yi Chen} and Huang, {Guo Wei}",

year = "2007",

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doi = "10.1109/APMC.2007.4554716",

language = "English",

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note = "null ; Conference date: 11-12-2007 Through 14-12-2007",

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AU - Wei, Hung Ju

AU - Meng, Chin-Chun

AU - Chang, Yu Wen

AU - Lin, Yi Chen

AU - Huang, Guo Wei

PY - 2007/12/1

Y1 - 2007/12/1

N2 - This paper demonstrates the Divide-by-4/5 prescalers with merged AND gates in 2 μm GaInP/GaAs heterojunction bipolar transistor (HBT) and 0.35 μm SiGe HBT technologies. By biasing the HBT near the peak transit-time frequency (fT), the maximum operating frequency of a D-type flip-flop (D-FF) can be promoted. At the supply voltage of 5 V, the GaInP/GaAs prescaler operates from 30 MHz to 5.2 GHz, and the SiGe prescaler has the higher-speed performance of 1 GHz ∼ 8 GHz at the cost of power consumption.

AB - This paper demonstrates the Divide-by-4/5 prescalers with merged AND gates in 2 μm GaInP/GaAs heterojunction bipolar transistor (HBT) and 0.35 μm SiGe HBT technologies. By biasing the HBT near the peak transit-time frequency (fT), the maximum operating frequency of a D-type flip-flop (D-FF) can be promoted. At the supply voltage of 5 V, the GaInP/GaAs prescaler operates from 30 MHz to 5.2 GHz, and the SiGe prescaler has the higher-speed performance of 1 GHz ∼ 8 GHz at the cost of power consumption.

KW - Divide-by-4/5

KW - Dual-modulus

KW - Emitter couple logic (ECL)

KW - GaInP/GaAs HBT

KW - Prescaler

KW - SiGe HBT

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