A high-speed dual-phase processing pipelined domino circuit design with a built-in performance adjusting mechanism

Ching Hwa Cheng*, Jiun-In  Guo

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A high-speed dual-phase domino circuit design with high performance and reliable characteristics is proposed. The cell-based automatic synthesis flow supports the quick design of high performance chips. The test chip of a dual-phase 64-bit high-speed multiplier with a built-in performance adjustment mechanism has been successfully validated using TSMC 0.18um CMOS technology. The test chip shows a 2.7X performance improvement compared to the conventional static CMOS logic design. In addition, a cell-based synthesizable design CAD flow, with consideration of the skew-tolerant issue has been established. A latched type domino cell library with noise-alleviation, charge sharing, and crosstalk alleviation abilities was also developed to support the proposed design flow. Finally, a built-in performance adjustment mechanism is conducted within the design. This mechanism supports performance adjustment after chip fabrication, under clock skew considerations.

Original languageEnglish
Title of host publication2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs
StatePublished - 25 Jul 2012
Event2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan
Duration: 23 Apr 201225 Apr 2012

Publication series

Name2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Conference

Conference2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
CountryTaiwan
CityHsinchu
Period23/04/1225/04/12

Keywords

  • performance adjustment
  • pipelined domino circuits

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    Cheng, C. H., & Guo, J-I. (2012). A high-speed dual-phase processing pipelined domino circuit design with a built-in performance adjusting mechanism. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers [6212635] (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). https://doi.org/10.1109/VLSI-DAT.2012.6212635