A high-performance multibit-flipping algorithm for LDPC decoding

Jui Hui Hung*, Sau-Gee Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

For LDPC decoding, bit-flipping (BF) algorithms are much simpler than the min-sum algorithms (MSA). However, BF algorithms have the disadvantages of poorer performances and higher iteration counts than MSA. This paper introduces the concepts of low correlation search and culprit vote to further improve the efficiency of the existing BF algorithms. High decoding performances and low iteration number are achieved by flipping those bits with low correlation as much as possible and introducing an additional syndrome vote procedure. As a result, the proposed algorithm can achieve significant decoding performance which is very close to the min-sum algorithm (MSA) but with much lower computation complexity.

Original languageEnglish
Title of host publicationISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings
Pages151-154
Number of pages4
StatePublished - 1 Dec 2009
Event12th International Symposium on Integrated Circuits, ISIC-2009 - Singapore, Singapore
Duration: 14 Dec 200916 Dec 2009

Publication series

NameISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings

Conference

Conference12th International Symposium on Integrated Circuits, ISIC-2009
CountrySingapore
CitySingapore
Period14/12/0916/12/09

Keywords

  • Bit-flipping algorithm
  • Channel coding
  • LDPC codes

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