A high-performance low V MIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control

Hao I. Yang*, Shih Chi Yang, Mao Chih Hsia, Yung Wei Lin, Yi Wei Lin, Chien Hen Chen, Chi Shin Chang, Geng Cing Lin, Yin Nien Chen, Ching Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan Chun Lien, Hung Yu Li, Kuen Di Lee, Wei Chiang Shih, Ya Ping Wu, Wen Ta Lee, Chih Chiang Hsu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

This paper describes a high-performance low V MIN SRAM with a disturb-free 8T cell. The SRAM utilizes single-ended buffer Read, and cross-point data-aware Write Word-Line structure with adaptive VVSS control to eliminate Read disturb and Half-Select disturb, thus facilitating bit-interleaving architecture and achieving low V MIN. A 512Kb test chip is implemented in UMC 55nm Standard Performance (SP) CMOS technology. The measurement results demonstrate operating frequency of 943MHz at 1.2V VDD and 209MHz at 0.6V VDD.

Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2011
Pages197-200
Number of pages4
DOIs
StatePublished - 28 Dec 2011
Event24th IEEE International System on Chip Conference, SOCC 2011 - Taipei, Taiwan
Duration: 26 Sep 201128 Sep 2011

Publication series

NameInternational System on Chip Conference
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Conference

Conference24th IEEE International System on Chip Conference, SOCC 2011
CountryTaiwan
CityTaipei
Period26/09/1128/09/11

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