A high performance liquid-nitrogen CMOS SRAM technology

J. Y.C. Sun; S. Klepner; Y. Taur; H. Hanafi; P. Restle; T. Bucelot; K. Petrillo; R. Dennard; S. Schuster; T. Chappell; B. Chappell; D. Heidel

A high performance liquid-nitrogen CMOS SRAM technology

J. Y.C. Sun^*, S. Klepner, Y. Taur, H. Hanafi, P. Restle, T. Bucelot, K. Petrillo, R. Dennard, S. Schuster, T. Chappell, B. Chappell, D. Heidel

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

A 3.5 ns ECL-compatible 64Kb liquid-nitrogen CMOS (LN-CMOS) SRAM technology with 2.5V power-supply voltage is described. Key features of this high performance 0.5μm-channel LN-CMOS SRAM technology optimized for 77K operation include 0.6,μm optical lithography for the gate level, dual polysilicon work functions, retrograde n-well, low resistance arsenic and boron source/drain diffusions, self-aligned titanium silicide, and two-level metal interconnects. For the first time, the leverage of liquid nitrogen CMOS with 2.3X chip level performance improvement at 77K over room temperature CMOS is demonstrated.

Original language	English
Title of host publication	ESSDERC 1988 - 18th European Solid State Device Research Conference
Editors	J.-P. Nougier, D. Gasquet
Publisher	IEEE Computer Society
Pages	C425-C428
ISBN (Electronic)	2868830994
ISBN (Print)	9782868830999
State	Published - 1988
Event	18th European Solid State Device Research Conference, ESSDERC 1988 - Montpellier, France Duration: 13 Sep 1988 → 16 Sep 1988

Publication series

Name	European Solid-State Device Research Conference
ISSN (Print)	1930-8876

Conference

Conference	18th European Solid State Device Research Conference, ESSDERC 1988
Country	France
City	Montpellier
Period	13/09/88 → 16/09/88

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Sun, J. Y. C., Klepner, S., Taur, Y., Hanafi, H., Restle, P., Bucelot, T., Petrillo, K., Dennard, R., Schuster, S., Chappell, T., Chappell, B., & Heidel, D. (1988). A high performance liquid-nitrogen CMOS SRAM technology. In J-P. Nougier, & D. Gasquet (Eds.), ESSDERC 1988 - 18th European Solid State Device Research Conference (pp. C425-C428). [5436845] (European Solid-State Device Research Conference). IEEE Computer Society.

Sun, J. Y.C. ; Klepner, S. ; Taur, Y. ; Hanafi, H. ; Restle, P. ; Bucelot, T. ; Petrillo, K. ; Dennard, R. ; Schuster, S. ; Chappell, T. ; Chappell, B. ; Heidel, D. / A high performance liquid-nitrogen CMOS SRAM technology. ESSDERC 1988 - 18th European Solid State Device Research Conference. editor / J.-P. Nougier ; D. Gasquet. IEEE Computer Society, 1988. pp. C425-C428 (European Solid-State Device Research Conference).

@inproceedings{d8bb51d9228f4692b7a8efc578ddb4c1,

title = "A high performance liquid-nitrogen CMOS SRAM technology",

abstract = "A 3.5 ns ECL-compatible 64Kb liquid-nitrogen CMOS (LN-CMOS) SRAM technology with 2.5V power-supply voltage is described. Key features of this high performance 0.5μm-channel LN-CMOS SRAM technology optimized for 77K operation include 0.6,μm optical lithography for the gate level, dual polysilicon work functions, retrograde n-well, low resistance arsenic and boron source/drain diffusions, self-aligned titanium silicide, and two-level metal interconnects. For the first time, the leverage of liquid nitrogen CMOS with 2.3X chip level performance improvement at 77K over room temperature CMOS is demonstrated.",

author = "Sun, {J. Y.C.} and S. Klepner and Y. Taur and H. Hanafi and P. Restle and T. Bucelot and K. Petrillo and R. Dennard and S. Schuster and T. Chappell and B. Chappell and D. Heidel",

year = "1988",

language = "English",

isbn = "9782868830999",

series = "European Solid-State Device Research Conference",

publisher = "IEEE Computer Society",

pages = "C425--C428",

editor = "J.-P. Nougier and D. Gasquet",

booktitle = "ESSDERC 1988 - 18th European Solid State Device Research Conference",

address = "United States",

note = "null ; Conference date: 13-09-1988 Through 16-09-1988",

}

Sun, JYC, Klepner, S, Taur, Y, Hanafi, H, Restle, P, Bucelot, T, Petrillo, K, Dennard, R, Schuster, S, Chappell, T, Chappell, B & Heidel, D 1988, A high performance liquid-nitrogen CMOS SRAM technology. in J-P Nougier & D Gasquet (eds), ESSDERC 1988 - 18th European Solid State Device Research Conference., 5436845, European Solid-State Device Research Conference, IEEE Computer Society, pp. C425-C428, 18th European Solid State Device Research Conference, ESSDERC 1988, Montpellier, France, 13/09/88.

A high performance liquid-nitrogen CMOS SRAM technology. / Sun, J. Y.C.; Klepner, S.; Taur, Y.; Hanafi, H.; Restle, P.; Bucelot, T.; Petrillo, K.; Dennard, R.; Schuster, S.; Chappell, T.; Chappell, B.; Heidel, D.

ESSDERC 1988 - 18th European Solid State Device Research Conference. ed. / J.-P. Nougier; D. Gasquet. IEEE Computer Society, 1988. p. C425-C428 5436845 (European Solid-State Device Research Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A high performance liquid-nitrogen CMOS SRAM technology

AU - Sun, J. Y.C.

AU - Klepner, S.

AU - Taur, Y.

AU - Hanafi, H.

AU - Restle, P.

AU - Bucelot, T.

AU - Petrillo, K.

AU - Dennard, R.

AU - Schuster, S.

AU - Chappell, T.

AU - Chappell, B.

AU - Heidel, D.

PY - 1988

Y1 - 1988

N2 - A 3.5 ns ECL-compatible 64Kb liquid-nitrogen CMOS (LN-CMOS) SRAM technology with 2.5V power-supply voltage is described. Key features of this high performance 0.5μm-channel LN-CMOS SRAM technology optimized for 77K operation include 0.6,μm optical lithography for the gate level, dual polysilicon work functions, retrograde n-well, low resistance arsenic and boron source/drain diffusions, self-aligned titanium silicide, and two-level metal interconnects. For the first time, the leverage of liquid nitrogen CMOS with 2.3X chip level performance improvement at 77K over room temperature CMOS is demonstrated.

AB - A 3.5 ns ECL-compatible 64Kb liquid-nitrogen CMOS (LN-CMOS) SRAM technology with 2.5V power-supply voltage is described. Key features of this high performance 0.5μm-channel LN-CMOS SRAM technology optimized for 77K operation include 0.6,μm optical lithography for the gate level, dual polysilicon work functions, retrograde n-well, low resistance arsenic and boron source/drain diffusions, self-aligned titanium silicide, and two-level metal interconnects. For the first time, the leverage of liquid nitrogen CMOS with 2.3X chip level performance improvement at 77K over room temperature CMOS is demonstrated.

UR - http://www.scopus.com/inward/record.url?scp=84907743191&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84907743191

SN - 9782868830999

T3 - European Solid-State Device Research Conference

SP - C425-C428

BT - ESSDERC 1988 - 18th European Solid State Device Research Conference

A2 - Nougier, J.-P.

A2 - Gasquet, D.

PB - IEEE Computer Society

Y2 - 13 September 1988 through 16 September 1988

ER -

A high performance liquid-nitrogen CMOS SRAM technology

Abstract

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