A high performance liquid-nitrogen CMOS SRAM technology

J. Y.C. Sun*, S. Klepner, Y. Taur, H. Hanafi, P. Restle, T. Bucelot, K. Petrillo, R. Dennard, S. Schuster, T. Chappell, B. Chappell, D. Heidel

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A 3.5 ns ECL-compatible 64Kb liquid-nitrogen CMOS (LN-CMOS) SRAM technology with 2.5V power-supply voltage is described. Key features of this high performance 0.5μm-channel LN-CMOS SRAM technology optimized for 77K operation include 0.6,μm optical lithography for the gate level, dual polysilicon work functions, retrograde n-well, low resistance arsenic and boron source/drain diffusions, self-aligned titanium silicide, and two-level metal interconnects. For the first time, the leverage of liquid nitrogen CMOS with 2.3X chip level performance improvement at 77K over room temperature CMOS is demonstrated.

Original languageEnglish
Title of host publicationESSDERC 1988 - 18th European Solid State Device Research Conference
EditorsJ.-P. Nougier, D. Gasquet
PublisherIEEE Computer Society
PagesC425-C428
ISBN (Electronic)2868830994
ISBN (Print)9782868830999
StatePublished - 1988
Event18th European Solid State Device Research Conference, ESSDERC 1988 - Montpellier, France
Duration: 13 Sep 198816 Sep 1988

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876

Conference

Conference18th European Solid State Device Research Conference, ESSDERC 1988
CountryFrance
CityMontpellier
Period13/09/8816/09/88

Fingerprint Dive into the research topics of 'A high performance liquid-nitrogen CMOS SRAM technology'. Together they form a unique fingerprint.

Cite this