A high performance CAVLC encoder design for MPEG-4 AVC/H.264 video coding applications

Chih Da Chien*, Keng Po Lu, Yi Hung Shih, Jiun-In  Guo

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

31 Scopus citations

Abstract

This paper presents a high performance VLSI architecture design for MPEG-4 AVC/H264 CAVLC encoding. In the proposed design, we propose a forward-based parallel coding (FPC) technique to increase the data throughput rate. Moreover, two approaches called arithmetic table elimination (ATE) and fast look-up table matching (FLM) are exploited to reduce the hardware cost. With the synthesis constraint of 125 MHz clock, the hardware cost of the proposed design is 9724 gates based on a 0.18um CMOS technology, which achieves the real-time processing requirement for H.264 video encoding on HD1080 format video.

Original languageEnglish
Title of host publicationISCAS 2006
Subtitle of host publication2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages3838-3841
Number of pages4
DOIs
StatePublished - 1 Dec 2006
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
Duration: 21 May 200624 May 2006

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

ConferenceISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
CountryGreece
CityKos
Period21/05/0624/05/06

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