A High-Performance 0.25-μm CMOS Technology: II—Technology

Bijan Davari, Wen Hsing Chang, K. E. Petrillo, C. Y. Wong, Dan Moy, Yuan Taur, Matthew R. Wordeman, Jack Yuan Chen Sun, Charles Ching Hsiang Hsu, Michael R. Polcari

Research output: Contribution to journalArticlepeer-review

52 Scopus citations

Abstract

In this paper, the key technology elements and their integration into a high-performance, selectively scaled, 0.25-μm CMOS technology are presented. Dual poly gates (n+ for nFET and p+ for pFET) are fabricated using a process, where the poly and source/drain (S/D) are doped simultaneously. The critical issues related to the dual poly gate, such as work function and boron penetration through thin gate oxide (7 nm) are addressed. A reduced operating voltage of 2.5 V is used which allows the application of shallow junctions with abrupt profiles (no LDD) to minimize the device series resistance as well as gate to source/drain overlap capacitance. The poly gate and the S/D sheet resistances are lowered, using a thin salicide (TiSi2) process. The TiSi2 thickness is reduced, as compared with the 0.5-μm CMOS process, to maintain the low leakage and low contact resistance for the shallow S/D junctions. To achieve low silicide sheet resistance, RTA processing is used, replacing the furnace anneals. The gate level with 0.4-μm physical length is defined using optical lithography with contrast enhanced layer (CEL) resist system. The CEL offers improved resolution and process control by producing vertical resist profiles down to the minimum dimensions. It also significantly reduces the interference effects and therefore the linewidth sensitivity to the resist thickness variations over topography.

Original languageEnglish
Pages (from-to)967-975
Number of pages9
JournalIEEE Transactions on Electron Devices
Volume39
Issue number4
DOIs
StatePublished - Apr 1992

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