In this paper a CMOS technology with the nominal channel length of 0.15 fim and minimum channel length below 0.1 μm is presented. Loaded NAND (FI=FO=3, CL,=240 fF) delay of 200 psec and unloaded delay of 33 psec at supply voltage of 1.8 V is demonstrated. In order to minimize short channel effects down to channel length below 0.1 μm, highly non-uniform channel doping obtained by indium and antimony, and source-drain extensions were utilized. To minimze the gate RC, a polycide stack gate structure was used.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|State||Published - 1993|
|Event||1993 13th Symposium on VLSI Technology, VLSIT 1993 - Kyoto, Japan|
Duration: 17 May 1993 → 19 May 1993