The proposed digital low-dropout regulator uses nonlinear switching control (NLSC) technique to suppress voltage ripple to less than 6 mV when the switching noise voltage of a switching regulator operating in a power-saving mode is greater than 50 mV. In addition, the NLSC technique improves the current efficiency by reducing the quiescent current to less than 10 μA and reduces the switching power loss through variable switching frequency control. With a load step of 1-20 mA, the transient response time is 1.3 μs and the peak current efficiency is 99.8% at heavy loads.
- Digital low-dropout regulator (DLDO)
- nonlinear switch control (NLSC) technique
- power-saving mode
- variable switching frequency control